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Have you written a testbench for this?
I also notice you missed the reset from the main process (will be important when testing).
I assume the failure is due to the extra pipeline delay when the extra idle state occurs. Is this acceptable in the design?
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I didn't write a testbench for this application. But what do you mean with a reset from the main process? I implemented a startup condition:
if(Reset_n = '0') then
STM_MAIN_CURR <= Step_Idle;
An extra delay is acceptable. In the future I want to add some logic in the extra IDLE step. This IDLE step will decide to jump to the READ or WRITE step based on external input. When read or write operation is finished the STM has to jump back to IDLE and later when an external read/write signal is set the logic in the IDLE step should start a new read or write process.
Thanks for the replies
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