Weird shift register behavior

I have a setup with two shift registers and a ram megafunction. All interfaces are 1 byte. The shift register takes in a serial stream, and then when writeEN is asserted, it parallel loads its data into RAM, and when readEn is asserted, the data is read out of an address in RAM and parallel loaded onto another shift register, and shifted out serially. The second shift register is acting strange in that its output isn't following the enable signals.

Here's what I have:

library ieee;
use ieee.std_logic_1164.all;
entity framestore is
	port
	(
		clk,reset : in std_logic;
		input: in std_logic;
		writeEN : in std_logic;
		readEN: in std_logic;
		rwAddress: in std_logic_vector(9 downto 0);
		output : out std_logic;
		writing : out std_logic_vector(7 downto 0);--test signal to keep track of what I write to memory
		reading : out std_logic_vector(7 downto 0)--test signal to see what I read from memory
	);
end framestore;
architecture structure of framestore is
	signal toRam: std_logic_vector(7 downto 0);
	signal fromRam: std_logic_vector(7 downto 0);
	
	COMPONENT rshift1byte IS --this is the first shift register, that has serial in, parallel out to ram
	PORT
	(
		aclr		: IN STD_LOGIC ;
		aset		: IN STD_LOGIC ;--sets to 0's
		clock		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	END COMPONENT;
	
	COMPONENT ram1port IS
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		clken		: IN STD_LOGIC  := '1'; --this enable is for the output port
		clock		: IN STD_LOGIC  := '1';
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
	END COMPONENT;
	
	COMPONENT rshift1byteout IS --this is the second shift register which has parallel in, serial out
	PORT
	(
		aclr		: IN STD_LOGIC ;
		aset		: IN STD_LOGIC ; --sets to 0's
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		load		: IN STD_LOGIC ;
		shiftout		: OUT STD_LOGIC 
	);
	END COMPONENT;
	
begin
	shiftin: rshift1byte port map(reset,reset,clk,input,toRam);
	ram: ram1port port map(rwAddress,readEN,clk,toRam,writeEN,fromRam);
	shiftout: rshift1byteout port map(reset,reset,clk,fromRam,readEN,output);
	
reading<=fromRam;
writing<=toRam;	
end structure;

reading and writing signals give the correct values, but they don't get shifted like they should in the output

Thanks!