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Honored Contributor
Honored ContributorWeird FIFO compiler error
I have an interesting error. I have a block diagram that I'm using to connect some symbols together that I've designed.
Here's an image of part of my block diagram: http://img134.imageshack.us/img134/977/weirdz.jpg I have a 4 bit output signal that comes from the block on the left and goes into the block on the right. I also have a 1 bit valid signal that does the same. Through trial an error I've found that if I take away that dangling wire, I get a compiler error that says: Error: WYSIWYG primitive "transmitinterface:inst11|fifo1to4:validbit|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_ecg1:auto_generated|altsyncram_sl61:fifo_ram|ram_block5a0" has mismatched parameters for port Port A, Data In Here's the code for transmitinterface
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity transmitinterface is
port
(
rdclk,wrclk,reset: in std_logic;
input: in std_logic_vector(3 downto 0);
validin: in std_logic_vector (0 downto 0);
validout: out std_logic;
output : out std_logic_vector(15 downto 0)
);
end transmitinterface;
architecture structure of transmitinterface is
signal hold : std_logic_vector(3 downto 0);
-------------------------------------
component fifo4to16 is
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
component fifo1to4 is
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
end component;
-------------------------------------
begin
inputbits: fifo4to16 port map(reset,input,rdclk,'1',wrclk,'1',output);
validbit: fifo1to4 port map(reset,validin,rdclk,'1',wrclk,'1',hold);
validout <= hold(3) OR hold(2) OR hold(1) OR hold(0);
end structure;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo1to4 IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END fifo1to4;
ARCHITECTURE SYN OF fifo1to4 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT dcfifo_mixed_widths
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
wrclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
intended_device_family => "Cyclone II",
lpm_numwords => 256,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 1,
lpm_widthu => 8,
lpm_widthu_r => 6,
lpm_width_r => 4,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4
)
PORT MAP (
wrclk => wrclk,
rdreq => rdreq,
aclr => aclr,
rdclk => rdclk,
wrreq => wrreq,
data => data,
q => sub_wire0
);
END SYN;
FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr, portaaddrstall, portabyteenamasks, portadatain, portawe, portbaddr, portbaddrstall, portbbyteenamasks, portbdatain, portbrewe)
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE)
RETURNS ( portadataout, portbdataout);
--synthesis_resources = M4K 1
OPTIONS ALTERA_INTERNAL_OPTION = "suppress_da_rule_internal=r105;OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SUBDESIGN altsyncram_sl61
(
aclr1 : input;
address_a : input;
address_b : input;
addressstall_b : input;
clock0 : input;
clock1 : input;
clocken1 : input;
data_a : input;
q_b : output;
wren_a : input;
)
VARIABLE
ram_block5a0 : cycloneii_ram_block
WITH (
CONNECTIVITY_CHECKING = "OFF",
DATA_INTERLEAVE_OFFSET_IN_BITS = 1,
DATA_INTERLEAVE_WIDTH_IN_BITS = 1,
LOGICAL_RAM_NAME = "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
OPERATION_MODE = "dual_port",
PORT_A_ADDRESS_WIDTH = 8,
PORT_A_DATA_WIDTH = 1,
PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
PORT_A_FIRST_ADDRESS = 0,
PORT_A_FIRST_BIT_NUMBER = 0,
PORT_A_LAST_ADDRESS = 255,
PORT_A_LOGICAL_RAM_DEPTH = 256,
PORT_A_LOGICAL_RAM_WIDTH = 1,
PORT_B_ADDRESS_CLOCK = "clock1",
PORT_B_ADDRESS_WIDTH = 6,
PORT_B_DATA_OUT_CLEAR = "clear1",
PORT_B_DATA_OUT_CLOCK = "clock1",
PORT_B_DATA_WIDTH = 4,
PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
PORT_B_FIRST_ADDRESS = 0,
PORT_B_FIRST_BIT_NUMBER = 0,
PORT_B_LAST_ADDRESS = 63,
PORT_B_LOGICAL_RAM_DEPTH = 64,
PORT_B_LOGICAL_RAM_WIDTH = 4,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
RAM_BLOCK_TYPE = "AUTO"
);
address_a_wire : WIRE;
address_b_wire : WIRE;
BEGIN
ram_block5a.clk0 = clock0;
ram_block5a.clk1 = clock1;
ram_block5a.clr1 = aclr1;
ram_block5a.ena0 = wren_a;
ram_block5a.ena1 = clocken1;
ram_block5a.portaaddr = ( address_a_wire);
ram_block5a.portadatain = ( data_a);
ram_block5a.portawe = wren_a;
ram_block5a.portbaddr = ( address_b_wire);
ram_block5a.portbaddrstall = addressstall_b;
ram_block5a.portbrewe = B"1";
address_a_wire = address_a;
address_b_wire = address_b;
q_b = ( ram_block5a.portbdataout);
END;
--VALID FILE
