We would like to export one signal from a connected interface in Platform designer.

A pipeline bridge has a master interface on one side and a slave on the other. So you would change something like this:

master -> slave

to something like this:

master -------> slave

|

----> slave (bridge) -> master (bridge; exported)

The bridge gets added to the address space of the master, so you have to make sure you set the bridge up with enough address bits. See this online training (it has other PD optimization techniques, but there is a slide on address coherency with pipeline bridges):

https://www.intel.com/content/www/us/en/programmable/support/training/course/oaqsysopt.html