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Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Ways to improve timing on Top module?

Say I have 3 modules: 1) Top module 2) sub-module A-(achieved freq 150Mhz when compiled separately) 3) sub-module B-(achieved freq 200 Mhz when compiled separately) After I instantiate sub-...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Do you have registers on the boundaries of your partitions? If you don't, then paths in the top level may become critical. Remember that there is no optimization across partition boundaries, so combinational logic on the boundaries of the design partitions cannot be optimized with respect to the top level.

Adding registers at the boundaries can fix this, allowing you to run the design faster at the expense of an extra cycle of latency.

#iwork4intel

Yogesh's avatar
Yogesh
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Yes , all output signals from a submodule are registers.

So before sending a signal to a other module , I am registering it .
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    Is the failing path within the sub-modules? Have you tried to preserve timing-closed partitions and use in the top design?

    Thanks.

    Best regards,

    KhaiY

    • Yogesh's avatar
      Yogesh
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago
      Hi,
      1) if I don't preserve design partition (fitter netlist of a submodule ) then yes , there are some failing paths within the submodule. Few days back fitter used to fail because of high routing congestion . So, I changed the fitter effort to 8.0 , so fitter passes but with significant loss of timing .

      2) If I preserve design partition(fitter netlist of the submodule ), then I don't think I have any critical paths within sub-modules . But there is inbetween 2 sub-modules. Here I get this fitter error sometimes :
      Error (18999): Placement cannot find a legal solution.
      Error (170079): Cannot place node <name>of type MLAB cell.
      But after changing fitter effort settings to 8.0 . It will pass with loss in timing.

      3)what does preserve timing closed partition mean ? Is it same as preserving fitter netlist in design partition? If yes , then yes I have done as in 2nd point