Warnings Altera has to fix

It annoys me that Altera supplied IP produces a massive amount of warnings. Making it almost impossible to find the one or two (important) ones generated by myself. An EP4CE55 design generates 1.9k (sic) warnings, try finding the needle in that haystack.

altera ip

Warning (12030): Port "afi_rrank" on the entity instantiation of "controller_inst" is connected to a signal of width 2. The formal width of the signal in the module is 4. The extra bits will be left dangling without any fan-out logic.

Warning (12020): Port "itf_rd_data_error" on the entity instantiation of "mm_st_converter_inst" is connected to a signal of width 2. The formal width of the signal in the module is 1. The extra bits will be ignored.

Warning (12011): Net is missing source, defaulting to GND

Warning (12110): Net "D12:u0|D12_ddr2:ddr2|D12_ddr2_controller_phy:D12_ddr2_controller_phy_inst|D12_ddr2_alt_mem_ddrx_controller_top:D12_ddr2_alt_mem_ddrx_controller_top_inst|itf_rd_data_error[1]" is missing source, defaulting to GND

You can find about twelve dozen of the above warnings if you instantiate an HPC DDR2 Controller.

avalon fabric

Warning (276027): Inferred dual-clock RAM node "D12:u0|D12_net:net|altera_avalon_mm_clock_crossing_bridge:bridge_mem|altera_avalon_dc_fifo:cmd_fifo|mem_rtl_0" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.

If you look up the help for it the Action: recommends To avoid receiving this message, apply the ramstyle synthesis attribute with the value "no_rw_check" to the RAM in your design file.

Warning (10269): Verilog HDL conditional expression warning at altera_avalon_st_pipeline_stage.sv(55): expression is wider than one bit

Warning (10862): input port "in_error[0]" at altera_avalon_st_pipeline_stage.sv(47) has no fan-out

Warning (10862): input port "clk" at D12_irq_mapper.sv(36) has no fan-out