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amildm's avatar
amildm
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3 years ago
Solved

Warning# for the port width mismatch

Hi All, What Warning Number is used to report the port width mismatches? How to know what warning messages were suppressed during the compilation? Why the synthesizer does not issue...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

Can you show some code?

amildm's avatar
amildm
Icon for Contributor rankContributor
3 years ago

Here is the code:

module rom_ver_num (
		output wire [31:0] q,       //       q.dataout
		input  wire [0:0]  address, // address.address
		input  wire        clock    //   clock.clk
	);
endmodule

rom_ver_num rtl_ver_num_i (.q(rtl_ver_num), .address(1'b0), .clock(clk));

As you can see, the rtl_ver_num signal is not declared (by mistake), so compiler interpretates it a single wire, but actually it should be a 32-bits wire (the same as the q signal width).

The Compiler has not issued any warning for this mismatch. Trying to understand why ...

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    I'm confused by your code. Are you instantiating rom_ver_num in something higher in the hierarchy or instantiating something else in rom_ver_num (below it)? Your code implies the latter, but you're doing the port mapping wrong. The signal names preceded by the dot (.) should be the lower level (module to instantiate) signals. I'm guessing you mean your instantiation to be something like this (don't know what the lower-level address signal name is so I call it addr):

    below_rom_ver_num rtl_ver_num_i (.rtl_ver_num(q), .addr(1'b0), .clk(clock));

    With this code, if rtl_ver_num does not exist as a signal, then you'd get an appropriate error. Since you've accidentally swapped the signal ordering in the port mapping, I'm not sure what's happening without seeing more code or exact warning messages in the tool.