Forum Discussion
ContributorWarning# for the port width mismatch
Here's the list of all the error and warnings messages.
As of now, I don't think we have tcl command for suppress message. The available tcl commands are also available on the same webpage.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.
Super ContributorCan you show some code?
amildmHere is the code:
module rom_ver_num ( output wire [31:0] q, // q.dataout input wire [0:0] address, // address.address input wire clock // clock.clk ); endmodule rom_ver_num rtl_ver_num_i (.q(rtl_ver_num), .address(1'b0), .clock(clk));As you can see, the rtl_ver_num signal is not declared (by mistake), so compiler interpretates it a single wire, but actually it should be a 32-bits wire (the same as the q signal width).
The Compiler has not issued any warning for this mismatch. Trying to understand why ...
- sstrell
I'm confused by your code. Are you instantiating rom_ver_num in something higher in the hierarchy or instantiating something else in rom_ver_num (below it)? Your code implies the latter, but you're doing the port mapping wrong. The signal names preceded by the dot (.) should be the lower level (module to instantiate) signals. I'm guessing you mean your instantiation to be something like this (don't know what the lower-level address signal name is so I call it addr):
below_rom_ver_num rtl_ver_num_i (.rtl_ver_num(q), .addr(1'b0), .clk(clock));
With this code, if rtl_ver_num does not exist as a signal, then you'd get an appropriate error. Since you've accidentally swapped the signal ordering in the port mapping, I'm not sure what's happening without seeing more code or exact warning messages in the tool.
