Forum Discussion
Hi,
Thanks for your update. I can see your update now. I believe you are posting them directly into the portal. I can see the demo_ncl.zip as well.
As I understand it from your notes, I understand that the design is passing Quartus compilation. Issue only occurs when you click on Verify Design. Also, I understand that there is no issue when you are running with different (older) versions of MATLAB and Quartus. Based on these observation, the issue seems to be related to interaction between the specific version of DSP Builder and Quartus but not the design or Quartus issue.
To avoid further gating your progress, you may try the following two workarounds tested working by you:
1. Running compilation with Quartus and then perform analysis on the compilation result without using Verify Design.
2. Try with the other setup of yours with MATLAB R2012a and Quartus V13.0.1 which is working.
At the same time, I will try to perform issue replication on my side. For your information, currently, I do not have the specific setup ie Q19.1Std and MATLAB R2013a installed in my PC. I will try with other version available in my PC to see if can replicate the observation. Once replicated, I will file a case to Factory for future fix.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin