Forum Discussion
Altera_Forum
Honored Contributor
10 years agoWarning during simulation using modelsim 10.4b
Hi all, While running a design verification generated via qsys testbench, I'm continuously monitoring sink bfm for any new data/packet. During this, i get this warning. *** warning: vl_init_v...
Altera_Forum
Honored Contributor
9 years agoI also saw this warning when I compiled a file by itself. I reran my compile script and it all worked again. I suggest playing with the compile order.