Forum Discussion
Occasional ContributorWarning (176441): The I/O pin <name> cannot meet the timing constraints due to conflicting require
You have -max on all 4 of your I/O contraints with no matching -min and you are using two different clock domains for all the same I/O pins, so the 2nd and 4th I/O constraints you have there are overriding the 1st and 3rd. You'll see this in the timing analyzer Ignored Constraints report.
On top of that, the referenced clocks for the inputs should be virtual clocks (the clock that drives the external device that then drives the inputs to the FPGA), and the clocks for the outputs should be either virtual (the clock at the downstream device capturing the outputs, assuming a synchronous interface) or the generated clock outputs of the PLL (if this is a source synchronous output interface).
Take a look at these trainings to find your scenario:
Occasional ContributorHow or why am I implementing a PLL compensated I/O?
I have not specified any special parameter in my SDC or Pin definition files that would cause that inference. The ALTLVDS_RX mega-function does not allow one to choose the type of PLL used in the design.
When I was designing my ALTLVDS_RX mega-function I entered the phase difference between the data and clock signals to be 90 degrees. Is this causing the said inference?
sstrellSuper Contributor
You have -max on all 4 of your I/O contraints with no matching -min and you are using two different clock domains for all the same I/O pins, so the 2nd and 4th I/O constraints you have there are overriding the 1st and 3rd. You'll see this in the timing analyzer Ignored Constraints report.
On top of that, the referenced clocks for the inputs should be virtual clocks (the clock that drives the external device that then drives the inputs to the FPGA), and the clocks for the outputs should be either virtual (the clock at the downstream device capturing the outputs, assuming a synchronous interface) or the generated clock outputs of the PLL (if this is a source synchronous output interface).
Take a look at these trainings to find your scenario:
