Occasional Contributor
Regular ContributorHi Sir,
When I checked your pin assignment, I see that you're not used the differential signal for clock.
I think that the clock should has ck and ck_n by referring to the example design.
Can you check about this as well?
And also there is no pll pin in the pin assignment.
How do you connect your pll in the design?
Regards,
Adzim
Occasional ContributorHi Thank you for taking a look at the project.
If you look in the pin planner you should see that input pin 'clock' is an LVDS signal connected to pins AA18 and AA19. The PLL is connected internally and 'clock' is the pll_reference signal. These are the same pins as the example project signal 'refclk_emif'. The 'clock' is connected to the 'emif_c10_0_pll_ref_clk_clk' signal of the DDR3 controller. This is the same way it is done in the example project.
As confirmation, the signal tap shows that 'pll_locked' does go high.
The calibration report should have been in the archived project. This forum will not allow me to upload .rpt files. I am uploading it as a .txt file, so hopefully it will work for you if you edit it back to .rpt.
