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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Warning (10492): But it's a clocked process

I don't understand why I have this warning.

Warning (10492): VHDL Process Statement warning at top.vhd(890): signal "sLS" is read inside the Process Statement but isn't in the Process Statement's sensitivity list

Testchip_process : process (iRESETb, iMCK1)

begin

if iRESETb = '0' then

oCPGA68_A7 <= sLS;

elsif rising_edge(iMCK1) then

case stoto is

when toto2 =>

oCPGA68_A7 <= sLS;

when Toto1 =>

oCPGA68_A7 <= '0';

when others => null;

end case;

end if;

end process Testchip_process;

It's a clocked process, I don't need to have sLS in process sensitivity

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    But you set the value of oCPGA68_A7 to sLS when you reset it. Hence you need it in the sensitivity list.

    Btw, this isnt a good thing to do. Reset value should be a fixed '0' or '1', or the synthesisor has to do some reset emulation, which isnt very good for timing.