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Altera_Forum's avatar
Altera_Forum
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11 years ago

vsim syntax error in wavefront file

Hi.

I'm following a simple example implementing a 4-bit full adder in Quartus II 14.0. When the circuit is ready for functional simulation, I create a wavefront file from the Simulation Wavefront Editor. In order to simplify the process to find the error I only add one of the A input nodes in the wavefront file - 1 single bit. Always forced to low to make it even simpler. I leave the rest of the signals for the moment.

When I run the functional simulation, the following messages are displayed:

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog Prova1 -c Prova1 --vector_source="C:/altera/14.0/Waveform_4bitadder.vwf" --testbench_file="C:/altera/14.0/simulation/qsim/Waveform_4bitadder.vwf.vt"

...

Completed successfully.

**** Generating the functional simulation netlist ****

quartus_eda --functional=on --flatten_buses=off --simulation --tool=modelsim_oem --format=verilog --output_directory="C:/altera/14.0/simulation/qsim/" Prova1 -c Prova1

...

Completed successfully.

**** Generating the ModelSim .do script ****

C:/altera/14.0/simulation/qsim/Prova1.do generated.

Completed successfully.

**** Running the ModelSim simulation ****

c:/altera/14.0/modelsim_ase/win32aloem//vsim -c -do Prova1.do

Reading C:/altera/14.0/modelsim_ase/tcl/vsim/pref.tcl

# 10.1e

# do Prova1.do

# ** Warning: (vlib-34) Library already exists at "work".

#

# Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013

# -- Compiling module \4bitadder

#

# Top level modules:

# \4bitadder

# Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013

# ** Error: Waveform_4bitadder.vwf.vt(30): near "4": syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or automatic or TYPE_IDENTIFIER or static

# ** Error: c:/altera/14.0/modelsim_ase/win32aloem/vlog failed.

# Executing ONERROR command at macro ./Prova1.do line 4

Error.

I'm going crazy trying to find the root cause of the error. Can anyone give me a hint on what is going on?

Thanks!

Enric

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Problem solved!

    The name of my .bdf file started by a number ("4bitadder.bdf"). It seems .bdf files must begin with a letter.

    Thanks anyway!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    This is because modelsim cannot simulation bdf files, they must be converted to VHDL or Verilog before simulation. In both of these languages identifiers must start with a letter.