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Altera_Forum
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11 years ago

vsim syntax error in wavefront file

Hi. I'm following a simple example implementing a 4-bit full adder in Quartus II 14.0. When the circuit is ready for functional simulation, I create a wavefront file from the Simulation Wavefro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

This is because modelsim cannot simulation bdf files, they must be converted to VHDL or Verilog before simulation. In both of these languages identifiers must start with a letter.