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I'll try to explain more on what i want
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I would prefer that you answer the questions I posed instead...repeated here since they are still necessary.
- Did you simulate the design? If so, what were the results? If not, get one and try it.
- What else did you try? What didn't work out as you wanted it to?
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depending on the input (sw) the register (sr) will assigned a collection of bits, also the signal (n) will be assigned an integer value which is the number of bits in the register, all of this will happen in the first process.
in the second process which is clocked i want it to shift the (sr) register for each rising edge clock (n) times.
here is what I've done:
<snip of partial code>
It's totaly wrong since two processes driving sr and n.
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OK, so you know what the problem is, you have two processes each driving a couple of signals...one would think then you know what to do which is to combine them into one process (hint: that's the answer)
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I know what I've done is stuped but I'm new to the vhdl and i came from another enviroment.
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It sounds like you know what the problem is, you can't have two drivers for one signal. So what is your question?
Kevin Jennings
Honored Contributor
