Honored Contributor
Honored ContributorI'll try to explain more on what i want , depending on the input (sw) the register (sr) will assigned a collection of bits, also the signal (n) will be assigned an integer value which is the number of bits in the register, all of this will happen in the first process.
in the second process which is clocked i want it to shift the (sr) register for each rising edge clock (n) times. here is what I've done: counter : process(clk) begin if rising_edge(clk) then if n/=0 then if sr(0)='0' then led <= "1111111"; elsif sr(0)='1' then led <= "0111111"; end if; n<=n-1; sr<="0" & sr(15 downto 1); end if; end if; end process; end behavioral; It's totaly wrong since two processes driving sr and n. I know what I've done is stuped but I'm new to the vhdl and i came from another enviroment.
