Virtual JTAG counter to TDO

This is the code easier :

module counterVjtag(
	// input
	input clock50,
	input key0, // reset for counter
	// output
	output  blinkLed
	);
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
	
// counter reg & wire
wire clk001;
reg  bigCounter;
reg  catchValue;
myPLL myPLL(
	.inclk0(clock50),
	.c0(clk001) // clock @ 10kHz
	);
// virtual JTAG reg & wire
reg tdo;
wire ir_in,ir_out;
wire tck;
wire v_cdr,v_sdr;
reg  dr1_tmp_reg;
assign ir_out = ir_in;
myvirtualJTAG myvirtualJTAG(
		// input
		.tdo(tdo),
		.ir_out(ir_out),	// 
		// output
		.tdi(),
		.ir_in(ir_in),	// 
		.virtual_state_cdr(v_cdr), 
		.virtual_state_sdr(v_sdr), 
		.virtual_state_e1dr(),
		.virtual_state_pdr(), 
		.virtual_state_e2dr(),
		.virtual_state_udr(), 
		.virtual_state_cir(), 
		.virtual_state_uir(), 
		.tms(),               
		.jtag_state_tlr(),    
		.jtag_state_rti(),    
		.jtag_state_sdrs(),   
		.jtag_state_cdr(),    
		.jtag_state_sdr(),    
		.jtag_state_e1dr(),   
		.jtag_state_pdr(),    
		.jtag_state_e2dr(),   
		.jtag_state_udr(),    
		.jtag_state_sirs(),   
		.jtag_state_cir(),    
		.jtag_state_sir(),    
		.jtag_state_e1ir(),   
		.jtag_state_pir(),    
		.jtag_state_e2ir(),   
		.jtag_state_uir(),    
		.tck(tck)               
	);
always @(posedge clk001)
begin
	if (key0)
		begin
			bigCounter = bigCounter + 1;
			catchValue = bigCounter ;	
		end
	else
		bigCounter = 0;
end
always @(posedge tck)
begin
	case (ir_in)
		0 :
			begin
				if(v_cdr)
					dr1_tmp_reg = catchValue;
				else
					if(v_sdr)
						begin
							tdo = dr1_tmp_reg;
							dr1_tmp_reg = dr1_tmp_reg >> 1;
						end
			end
	endcase
end
endmodule

module counter (clock, my_counter);
input clock;
output  my_counter;
reg  my_counter;
always @ (posedge clock)
 if (load && e1dr) // decode logic: used to load the counter my_counter
 my_counter <= tmp_reg;
 else
 my_counter <= my_counter + 1;
// Signals and registers declared for VJI instance
wire tck, tdi;
reg tdo;
wire cdr, eldr, e2dr, pdr, sdr, udr, uir, cir;
wire  ir_in;
// Instantiation of VJI
my_vji VJI_INST(
 .tdo (tdo),
 .tck (tck),
 .tdi (tdi),
 .tms(),
 .ir_in(ir_in),
 .ir_out(),
 .virtual_state_cdr (cdr),
 .virtual_state_e1dr(e1dr),
 .virtual_state_e2dr(e2dr),
 .virtual_state_pdr (pdr),
 .virtual_state_sdr (sdr),
 .virtual_state_udr (udr),
 .virtual_state_uir (uir),
 .virtual_state_cir (cir)
);
// Declaration of data register
reg  tmp_reg;
// Deocde Logic Block
// Making some decode logic from ir_in output port of VJI
wire load = ir_in && ~ir_in;
// Bypass used to maintain the scan chain continuity for
// tdi and tdo ports
bypass_reg <= tdi;
// Data Register Block
always @ (posedge tck)
 if ( load && sdr )
 tmp_reg <= {tdi, tmp_reg};
// tdo Logic Block
always @ (tmp_reg or bypass_reg)
 if(load)
 tdo <= tmp_reg
else
 tdo <= bypass_reg;
endmodule