virtual clock source latency

You might have hit my problem here... Let me elaborate and see ;)

I'm trying to constrain an output path that is basically running without a clock in the STA sense (software might create one by bit banging).

So all I can try is to limit the time from this software driven register to the output pin.

Picking up your example, the 15ns clock delay possibly applies to all registers driving output pins. In that case, I would not mind if the sum of clock delay, data delay and external setup is bigger than one period, as long as the sum of data delay and external setup is not.

But probably my assumption of having the same clock delay to all output registers is rather daring.

Also, the idea to constrain something rather asynchronous below one clock period seems somewhat strange in that light. So I can easily use a multicycle and assume that no one ever tries to send data faster.

Maybe my thoughts here are not very clear... Maybe I'm just not smart enough for STA and SDC...