Viewing variable values in VHDL

I wasn't aware of anything specific to Verilog in ug_ram.pdf. If it's the case with instantiation examples, they can be done with VHDL as well. To my opinion, the equivalence of Verilog and VHDL should be almost obvious. RAM inference from VHDL code is also discussed in the "book", the complete Quartus II handbook.

With oe, I meant the output enable port of IO cells, that comes into play with bidirectional or threestate outputs. It exists in the synthesized logic, although it's not a signal in your code. It's helpful to my opinion, to consider that your logic must be able to drive an output enable and what should be it's timing.

I didn't exactly understand what's the purpose of your RAM design. Due to the synchronous nature of FPGA internal RAM, particularly the registered input signals, you can't model an asynchronous RAM this way. An appropriate design depends on the timing of the external bus. I have examples, where an internal RAM is connected to an asynchronous processor bus. But a bus cycle has a duration of serveral FPGA clocks in this case. I'm using explicite altsyncram instances rather than inference from VHDL, cause I need additional features as dual port with different word widths that can't be inferred from HDL.