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Altera_Forum's avatar
Altera_Forum
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17 years ago

Viewing variable values in VHDL

Hi, I am quite new to VHDL and Quartus II. I have coded a 16x8 RAM using VHDL in Quartus but I don't know how to check it because I cannot view the array variable where the data is stored in wa...
Altera_Forum's avatar
Altera_Forum
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17 years ago

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It should be also possible to operate your RAM example with a bidirectional data port. The bidirectional IO cells have separate in- and output port at the FPGA side, all you need is an output enable signal with correct timing. This implies for synchronous solution, that the inout port must been set to 'Z' (= OE deasserted) one clock cycle before the input data can be latched. Alternatively, OE can be operated asynchronously from RW signal.

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Thanks..

Umm, I don't quite get it on the OE and RW part especially "OE can be operated asynchronously from RW signal".. Is OE different from RW..?

Can you please advice how I can convert the code in Post# 16 (using seperate DataIn and DataOut port) into a code that is using bidirectional port..?

Maybe, can you modify the existing code from Post# 16 as an example..? I understand better from examples..

Thanks and thanks again..