Viewing variable values in VHDL

A detailed explaination of FPGA internal RAM timing can be found in the RAM Megafunction user guide. It's particularly helpful to understand the available option when infering Megafunction from HDL, as you did in your example.

It should be also possible to operate your RAM example with a bidirectional data port. The bidirectional IO cells have separate in- and output port at the FPGA side, all you need is an output enable signal with correct timing. This implies for synchronous solution, that the inout port must been set to 'Z' (= OE deasserted) one clock cycle before the input data can be latched. Alternatively, OE can be operated asynchronously from RW signal.

P.S.: As you already find out, the Quartus integrated simulator isn't able to display RAM cell internal data. This can be done very comfortable with ModelSIm. The Megafunction user guide shows also ModelSim simulation examples.

It isn't generally necessary to invert your address bit direction to

Addr <= (A3 & A2 & A1 & A0);

as suggested cause the same permutation is in effect for read and write, but the reversed bit order may cause confusion when analyzing simulation results with interger addresses.