Viewing variable values in VHDL

I didn't realised that you have posted.. Thanks..

I was too busy trying to figure out.. I think I've managed to get it work but instead of using "Data : inout std_logic_vector", i seperate it into "DataIn : in..." and "DataOut : out..."

My guess is if I use "Data : inout", Quartus doesn't know whether that pin at that particular instance is either input or output and if I assign 2 different signals to it (1 from external input and another from internal assignment) without adding more code to latch it, it just wont work..

However, below is the updated code and the resulted waveform.

From the resulted waveform, i think the writing process happens at the 'next clock pulse' while the reading process happens at the 'current clock pulse'. In the waveform, at the 4th clock pulse, eventhough R_Wbar is HIGH, the data "00001111" is still written into Address "1000" because at the 8th clock pulse, "00001111" is read out from Address "1000".

library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM is 
    port (     A0,A1,A2,A3    : in std_logic;
               CS        : in std_logic;
            clk        : in std_logic;
               R_Wbar     : in std_logic;
               DataIn    : in std_logic_vector (7 downto 0);
            DataOut    : out std_logic_vector (7 downto 0));
end RAM;
Architecture version1 of RAM is
    signal Addr : unsigned (3 downto 0);
    type MEM is array (15 downto 0) of std_logic_vector (7 downto 0);    
    signal MEM_s : MEM;
    
Begin
    Addr <= (A0 & A1 & A2 & A3);
    
    Process    (clk)
    
        variable Addr_int : integer;
    
    Begin
        if Rising_Edge(clk) then
            Addr_int := TO_INTEGER(Addr);
            if (CS = '0') then
        
                if (R_Wbar = '0') then 
                    MEM_s(Addr_int) <= DataIn;
                  elsif (R_Wbar = '1') then
                    DataOut <= MEM_s(Addr_int) ;
                end if;
            else
                DataOut <= "ZZZZZZZZ";
            end if;
        end if;
    End process;
End version1;