[VHDL&Quartus] Merging registers

This is the code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
    ext_ram_address: OUT std_logic_vector (18 DOWNTO 0);
    signal ram_address_rd:  std_logic_vector (18 DOWNTO 0);
    signal address_count_proc1: integer range 0 to 524287;
    signal address_count_wr: integer range 0 to 524287;
ram_address_rd <= std_logic_vector(to_unsigned(address_count, 19));
address_count <= address_count_proc1 when ram_read_selector = '0' else address_count_wr;
PROCESS (clock100, ram_address_rd)
begin
if rising_edge(clock100) then
ext_ram_address <= ram_address_rd;
end if;
end process;

address_count_proc1 and address_count_wr are two register witout any relationship.

When i check with the oscilloscope the content of ext_ram_address it seems that the content of address_count_wr is copied with the wrong direction (MSB as LSB and LSB as MSB).