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Altera_Forum's avatar
Altera_Forum
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11 years ago

VHDL2008 matching equality operator

i can't get VHDL-2008 matching equality operator compiled on quartus2. when i compile the code below it says: Error (10327): VHDL error at test.vhd(13): can't determine definition of operator "...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Hi Tricky,

Tried Modelsim (starter 10.3d) and it turned out it's not happy with the code as well, saying :

Signal "a" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type ieee.std_logic_1164.STD_LOGIC.

I double checked the the env variable VHDL93 has been chanted to 2008 in modelsim.ini file.

It looks pretty much like what you've said. I'll raise a flag to Altera.

Thanks for your help.