VHDL2008 matching equality operator

Thanks for the replies!

Actually what I did at the first place was declaring y as std_logic, but seems it somehow got messed up when I copied the code to the thread. ('&nbsp' appeared as burried backspaces in the source file? I don't know).

I also had tried std_ulogic(_vector) but no difference.

I tried the following code just in case but again got the same error message for both y and z(0).

library ieee;

use ieee.std_logic_1164.all;

entity meqtest is

port(

a,b: in std_logic_vector(2 downto 0);

y: out std_logic;

z: out std_logic_vector(1 downto 0)

);

end meqtest;

architecture rtl of meqtest is

begin

y <= a ?= b;

z(0) <= a ?= b;

end rtl;

Thanks again,