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The assignment Y <= t2; being outside clock edge is firstly very uncommon
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Whether it is uncommon doesn't matter. It is valid VHDL. (neither QuartusII nor ModelSim complained ...) This method allows you to make a Mealy state machine factoring in the inputs after the clocked process. Very concise, everything in one process. (That does appeal to you, doesn't it?)
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Secondly it implies that t2 drive Y whether t2 is assigned inside clock construct or occurs outside. We know that if clock edge occurs then t2 is assigned but if clock edge is not true then t2 must retains its value and this implies registered version of t2 to drive Y
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Saying it simpler: "Any output leaving a clocked process (the part between the '
if rising_edge() then' and the matching '
end if ;' or as you call it '
inside the clock edge' ) will be registered".
I'm not sure whether all VHDL compilers will generate the same RTL. I couldn't find any specifics on that in the LRM, but I only did a quick text search for
variable.
Honored Contributor
