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Josyb can you please try doing again test3 but now with using another variable t2 to store t1 before setting Yb?
process(clk)
variable t1 : std_logic;
variable t2 : std_logic;
begin
if rising_edge(clk) then
t1 := A and B;
t2 := t1;
Yb <= t1;
end if;
Y <= t2; -- does this attempt fail to export asynchronous t2?
end process;
Can you do this test and provide the RTL diagram again?
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t2 will be just wired to t1.
The assignment Y <= t2; being outside clock edge is firstly very uncommon. Secondly it implies that t2 drive Y whether t2 is assigned inside clock construct or occurs outside. We know that if clock edge occurs then t2 is assigned but if clock edge is not true then t2 must retains its value and this implies registered version of t2 to drive Y
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