VHDL Variables: Is it combinational code inside a clocked process?

The assignment C <= t1 ; reads t1 before t1 is assigned to, hence it infers a register

The assignment D <= t1 ; reads t1 after t1 has been assigned with 'A and B' hence D is fed with the combinatorial

The assignment E <= t1 ; also infers a register, but in this case this is not visible as the compiler can re-use the previously inferred register (from C <= t1; )

Splitting the example over the three different assignments shows it better:

-- test1------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test1 is
	Port(clk : in  std_logic;
		 A   : in  STD_LOGIC;
		 B   : in  STD_LOGIC;
		 Y   : out STD_LOGIC);
end test1;
architecture rtl of test1 is
begin
	process(clk)
		variable t1 : std_logic;
	begin
		if rising_edge(clk) then
			Y  <= t1;                   -- read first
			t1 := A and B;
		end if;
	end process;
end rtl;
-- test2------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test2 is
	Port(clk : in  std_logic;
		 A   : in  STD_LOGIC;
		 B   : in  STD_LOGIC;
		 Y   : out STD_LOGIC);
end test2;
architecture rtl of test2 is
begin
	process(clk)
		variable t1 : std_logic;
	begin
		if rising_edge(clk) then
			t1 := A and B;              -- assign first
			Y  <= t1;
		end if;
	end process;
end rtl;
-- test3------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test3 is
	Port(clk : in  std_logic;
		 A   : in  STD_LOGIC;
		 B   : in  STD_LOGIC;
		 Y   : out STD_LOGIC;
		 Yb  : out std_logic);
end test3;
architecture rtl of test3 is
begin
	process(clk)
		variable t1 : std_logic;
	begin
		if rising_edge(clk) then
			t1 := A and B;
			Yb <= t1;
		end if;
		Y <= t1;                        -- attempt to produce a comb output fails
	end process;
end rtl;
-----------------------------
-- all
-----------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test is
	Port(clk             : in  std_logic;
		 A               : in  STD_LOGIC;
		 B               : in  STD_LOGIC;
		 Y1, Y2, Y3, Y3b : out STD_LOGIC);
end test;
architecture rtl of test is
begin
	t1 : entity work.test1 port map(clk => clk, A => A, B => B, Y => Y1);
	t2 : entity work.test2 port map(clk => clk, A => A, B => B, Y => Y2);
	t3 : entity work.test3 port map(clk => clk, A => A, B => B, Y => Y3, Yb => Y3b);
end rtl;
 

producing this RTL Viewer image: