VHDL Variables: Is it combinational code inside a clocked process?

As you an see even though

C <= t1;

D <= t1;

literally means both are driven by t1 but not exactly in sequential sense. first t1 implied registered version of t1 (or say after process update in software mindset)

regarding name of register, the habit is to name it by its output and not by its input and if you search for t1 reg in timequest I doubt you will find it.

On the other hand the counter example I gave above gives more insight into behaviour of variables:

if counter is variable or signal you end up with same counting logic (adder and register) but the test logic is put on different nodes. For variable count the test logic is on the count node (i.e. input to register). For signal count the test is on count node again (but is now output of register).

by the way the statement:

count := count + 1; is similar to the case of reading variable before its assignment.