VHDL Variables: Is it combinational code inside a clocked process?

From my observation a variable always means:

(1) combinatorial logic for the given assignment even though it is inside clocked process. Thus

t1 := A and B;

y <= t1;

means just that t1 is output of ANDed A,B without any register(no clock period delay) .

y is a register on output of ANDed inputs

(2) in the case t1 is read before its assignment e.g.

C <= t1;

t1 := A AND B;

then

C is obviously registered. t1 is not but the tool understands t1 to keep its last value which is to be assigned later so a further register is added to save t1 for C assignment leading to two registers (one is named C, the other one on t1 is not known as t1 to the tool since t1 refers to the combinatorial node but this might depend on tool)

regarding my example (count integer range 0 to 99), yes it should be 0 to say anything suitable more than 99.