VHDL Variables: Is it combinational code inside a clocked process?

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You are right but I think it's a matter of readibility and avoiding mistakes.

I find it more easy to read splitting the RTL into a combination process and a sequential process. So, no need for variable. when you need the _next value(comb) right away in the sequential process just use the LVALUE (next) in the decision making.

It's always harder to spot errors in simulation using Variables and simulation/synthesis mismatch ocurrs more.

YMMV

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I don't know of any mismatch between tools regarding variables as long as they conform to vhdl standards.

One case when I need to use variable is modulo n accumulator when n is not power of 2.

For example if I need to add 7 modulo 100. I need to prevent counter going > 99 so I need to use variable to check value of counter and force it:

variable count : integer range 0 to 99 := 0;
begin
...
if count > 99 then
    count := count -100;
else
   count := count + 7;
end if;
...

if you use signal then count will be > 99 for one sample. Here one cay use if (count + 7) > 99... but I prefer variable