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Oh. Another question came up though.
What happens when the designer wants to export asynchronously a variable from a clocked process?
Declaring a signal and assigning it to the variable inside the clocked process would infer a register...
I suppose doing the assignment after the "clocked" IF, ELSEIF(rising edge) would still keep the signal asynchronous...right?
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No. I just modified my 'contrived' example to try this out.
--variables.vhd
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity variables is
port(
Clk : in std_logic;
Reset : in std_logic;
A : in natural range 0 to 255;
B : in natural range 0 to 255;
C : in natural range 0 to 255;
Y : out natural range 0 to 1023;
Y5 : out natural range 0 to 255;
Y2 : out natural range 0 to 255;
Y3 : out natural range 0 to 511;
Y4 : out natural range 0 to 1023
);
end variables;
architecture arch of variables is
begin
process ( Clk , Reset , A, B) is
variable t0 : natural range 0 to 255 ;
variable t1 : natural range 0 to 255 ;
variable t2 : natural range 0 to 511 ;
variable t4 : natural range 0 to 255 ;
begin
if (Reset = '1') then
Y <= 0 ;
t2 := 0 ;
elsif rising_edge( Clk ) then
Y <= t2 + C ;
if (A > B) then
t1 := A ;
t0 := B ;
else
t1 := B ;
t0 := A ;
end if ;
t2 := t0 + B ;
end if;
Y2 <= t1 ;
Y3 <= t2 ;
Y4 <= t1 + t2 ;
if (A > B) then
t4 := A ;
else
t4 := B ;
end if ;
Y5 <= t4 ;
end process ;
end arch ;
In variables3.pdf you can see what happens:
Honored Contributor
