VHDL Variables: Is it combinational code inside a clocked process?

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Hello all

I was wondering, in order to make the code more readable and maintanable, is it possible to use variables to implement the complicated combinational code inside the clocked process so that I do not have to use another non-clocked process?

Since I havent found somewhere a clear answer about the use of variables, I wanted to ask, is that the purpose of existence of VHDL variables? Do variables exist in order simplify the writing of combinational code inside a clocked process?

Note: If I used signals inside the clocked process to help me store intermediate results,that would lead to register inference which is not intended if the designer wants to implement pure combionational code inside the clocked process.

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That is one of the 'great' uses of variables: splitting up a long series of complicated comb code inside a clocked process over multiple lines. The other use is: instead of declaring globally visible 'signals' which are only used in this process, you can declare variables locally and make them infer registers.

You have perfect control whether a variable infers registers or not: if you assign to the variable first before 'reading' it, no registers will be inferred.

I made a 'contrived' example:

--variables.vhd
library ieee ;
	use ieee.std_logic_1164.all ;
	use ieee.numeric_std.all ;
entity variables is
	port(
		Clk   : in  std_logic;
		Reset : in  std_logic;
		A     : in  natural range 0 to 255;
		B     : in  natural range 0 to 255;
		C     : in  natural range 0 to 255;
		Y     : out natural range 0 to 1023
	);
end variables;
architecture arch of variables is
begin
	process ( Clk ,  Reset ) is
			variable t1 : natural ; -- combinatorial
			variable t2 : natural ; -- registered
		begin
			if (Reset = '1') then
				Y <= 0 ;
			elsif rising_edge( Clk ) then
				Y <= t2 + C ; -- this will infer registers for t2
				if (A > B) then
					t1 := A ;
				else
					t1 := B ;
				end if ;
				t2 := t1 + B ;
			end if;
		end process ;
end arch ;

If we run this through the Analysis & Synthesis we see the following in the RTL Viewer: see .pdf attached.

You can see the combinatorial logic for 't1' and the inferred registers for 't2'.