VHDL type mismatch error

Hello to everybody.

Please someone could tell me where is the error in the following VHDL code?

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity round16to12 is

port

(

a : in std_logic_vector(15 downto 0);

q : out std_logic_vector(11 downto 0)

);

end entity;

architecture beh of round16to12 is

19 begin

20

21 process(a)

22 begin

23

24 q <= (11 => not(a(15)), others => a(14 downto 4) );

25 end process;

26

27 end beh;

Quartus II 7.2 sp1 web edition gives me the following error:

Error (10381): VHDL Type Mismatch error at round16to12.vhd(24): indexed name returns a value whose type does not match "std_ulogic", the type of the target expression

I really don't understand the reason of that message.

Thanks for your support