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Altera_Forum's avatar
Altera_Forum
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11 years ago

VHDL Type Mismatch error

Hi,

I have attached to this message two files that I am trying to compile (bus_relay.vhd and bcff.vhd).

The problem is that the file bcff.vhd which is the top level entity will not compile. It keeps giving me an error message of (Error (10381): VHDL Type Mismatch error at bcff.vhd(46): indexed name returns a value whose type does not match "std_logic_vector", the type of the target expression).

Could you please look at the two files for me and try to fix the bug.

Also I want to know if the current design has the bus_relay pass signals from IO1 to IO2 and vice versa. I am not sure that the signal is propagating properly. Would you look into this for me and fix the error.

Thanks.

Lewis.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    nice error, since the file only has 44 lines.

    [edit]

    you assign a single bit to a std_logic_vector and that is not valid.

    [/edit]
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    indexing into an array gives you a single element of the array, which in this case is a std_logic. The component expects a std_logic_vector of length 1 (because N defaults to 1). So you need to pass it:

    LIN(0 downto 0)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    indexing into an array gives you a single element of the array, which in this case is a std_logic. The component expects a std_logic_vector of length 1 (because N defaults to 1). So you need to pass it:

    LIN(0 downto 0)

    --- Quote End ---

    Hi.

    Thanks for the feedback.

    Could you give me an example in the form of the full source code.

    Thanks.