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Altera_Forum's avatar
Altera_Forum
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11 years ago

VHDL Type Mismatch error

Hi, I have attached to this message two files that I am trying to compile (bus_relay.vhd and bcff.vhd). The problem is that the file bcff.vhd which is the top level entity will not compile. It k...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

nice error, since the file only has 44 lines.

[edit]

you assign a single bit to a std_logic_vector and that is not valid.

[/edit]