Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

VHDL trouble

Hi,

I seem to be getting continuous errors with if statements in Quartus but cannot see a problem at all could someone please help here?

Code:

if (ip(1) xor ip(2) xor ip(3) xor ip(4) xor ip(5) xor ip(6) xor ip(7)) = '0' then error <= '0';

else error <= '1';

end if;

ip is declared as "in std_logic_vector(7 downto 1)"

error is a signal of std_logic

The errors I'm receiving are:

Error (10500): VHDL syntax error at hamming_decode.vhd(20) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at hamming_decode.vhd(20) near text "="; expecting "<="

Error (10500): VHDL syntax error at hamming_decode.vhd(21) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement

Error (10500): VHDL syntax error at hamming_decode.vhd(22) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"

I seem to get these errors anytime I attempt an if statement. I've tried changing many things including declaring the value of the XOR sum as a check and writing:

if check = '0' then.....

to no avail of course.

Does Quartus even support if statements in VHDL or only in AHDL??

Any help seriously appreciated.

Thanks

Maria

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    It supports "if" statements in VHDL.

    Why is it giving you such errors, no clue. Maybe it's something before those lines? Parsers can ocasionally be dumb and point you to the wrong place.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Thanks for the reply,

    I wrapped the statements in a process statement and it seemed to the trick, I don't particularly understand why but will clarify it in college hopefully.

    Thanks again,

    Maria
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Its not hard to find syntax errors,pay more attention to the errors, you'll find them somewhere else.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    I don't particularly understand why

    --- Quote End ---

    The difference betwen concurrent and sequential statements (processes) is a basic VHDL concept. Other languages as Verilog have similar concepts. It you intend to work seriously with VHDL, you should learn about it. As a first step, you can get the mere syntax rules from the Quartus Editor's language templates. ("Insert template" in the editor context menu).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    --- Quote Start ---

    Thanks for the reply,

    I wrapped the statements in a process statement and it seemed to the trick, I don't particularly understand why but will clarify it in college hopefully.

    Thanks again,

    Maria

    --- Quote End ---

    That will be your problem. You cannot use if outside of the process because it is a sequential statment.

    The other way to do it is to use conditional assignment: 

    
use ieee.std_logic_misc.all; --for reduce function
.....
--later outside a process:
error <= '0' when xor_reduce(ip) = '0' else '1';
--but looking at your code, all that means is:
error <= xor_reduce(ip);