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Altera_Forum's avatar
Altera_Forum
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12 years ago

VHDL TestBench syntax

Hi ,

what is the VHDL TestBench syntax to assert input port: seed_en='0' (from 0ns) and after 30ns assert to seed_en='1' and after 10ns(30+10=40) assert to seed_en='0' and keep it at '0' .

Thanks .

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    one way is usign process:

    process

    begin

    seed_en = '0';

    wait for 30ns;

    seed_en = '1';

    wait for 10ns;

    seed_en = '0';

    wait for .... -- write here the time until the end of simulation;

    assert false

    report "Simulation Completed"

    severity failure;

    end process;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You can also use the "after" keyword 

    
seed_en <= '0', '1' after 30 ns, '0' after 40 ns;

    Cheers,

    Dave