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Altera_Forum
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13 years ago

VHDL Syntax Questions - State Machine

Hello everyone, working on a class assignment and am struggling with VHDL syntax. I am getting the following error: Error (10500): VHDL syntax error at SM_VHDL.VHD(79) near text "ELSE"; expecting...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Thanks, I have changed it to this: 


Z  <= '1' WHEN state = A ELSE '0';
    Q  <= "00" WHEN state = A ELSE
          "01" WHEN state = B ELSE
          "10" WHEN state = C;

And I am now getting the following errors:

Error (10313): VHDL Case Statement error at SM_VHDL.VHD(25): Case Statement choices must cover all possible values of expression.

Each case takes into account all 4 binary combinations however... Hmm.