VHDL Simulation Timing Errors

Hi all,

I have been working on a VHDL project of my own and have been having some simulation issues I have been trying to resolve with no luck of my own. So here is the break down:

It is a package of functions, procedures and components, the main break down is that there are components that have multiple architectures that call different procedures (which all accept and output signals an example is below).

ex: procedure test (signal Ai, Bi : IN [TYPE]; signal Ao, Bo : OUT [TYPE])

Type is a custom multiple-valued logic system that I have created (7 state logic system).

These procedures resolve logical operations based on 2-Dimensional arrays and return values on an inertial delay model (unless an input is being passed as an output in which transport is used). I have verified that the logic from the operations resolves correctly the only issue is that the operations aren't simulating with proper timing for some instances and inputs greater than 2 variables, I have tried making concurrent instances with procedural operations, I have tried all procedural operations, and just about everything I can think of working the ins and outs of VHDL. so the final issue a small example:

Timing.... If I call 2 separate procedures that resolve their logic operations from two different 2D-arrays each of which output their signals 1ns after the value is returned from the array. When using 2 structures the simulation delay is shown as 1ns when it should be 2ns. The second issue is when using a 3rd input line to a separate structure that is composed of these base structures timing is off; for example say there is a structure:

"ENTITY Turtle IS

PORT (Ai, Bi, Ci : IN [TYPE]; Ao, Bo, Co : OUT [TYPE]);

END ENTITY;"

Architecture struct of Turtle is

signal ta, tb, tc : [TYPE];

signal ta1, tb1, tc1 : [TYPE];

begin

Box1(Ai,Bi,ta,tb);

Box2(ta,Ci,ta1,tc);

Box3(tb,tc,tb1,tc1);

Ao <= ta1;

Bo <= tb1;

Co <= tc1;

-- I have also tried removing signal assignment and having the procedures directly output to the entity output signals (this made no difference).

end struct;

That uses these procedures, and the delays of Ao, Bo, Co are supposed to be 3ns, 5ns, and 5ns, respectively (Its based on timing delays from Box1, Box2, and Box3). Simulation of the structure returns the proper timing of Ao but the delay on Bo(5ns) actually varies from 3ns to 4ns, and the same with Co(5ns) it varies 3ns to 4ns but during simulation at a point it outputs at 3ns with the incorrect logic, then 1ns later updates to the correct logic value on the output.

If tried event statements, enable statements, postponed processes, completely procedural methods and component based methods, all with no luck.

Any ideas or ways to resolve this issue? All help is greatly appreciated and will be acknowledged. I will try to be as helpful as possible with further descriptions, but prefer not to post images or sample code.

Thanks,

BodeL