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Altera_Forum
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14 years ago

VHDL Simulation Timing Errors

Hi all, I have been working on a VHDL project of my own and have been having some simulation issues I have been trying to resolve with no luck of my own. So here is the break down: It is a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ouch, well, while I understand this is an altera forum, I don't believe ISim or Xilinx tools to be my problem, I came here in search of VHDL based help which is where I believe my errors to be. It will take sometime but I can compile a single file that should run, if you pm me your email or method of delivering you the file I can give it to you, its just not something I want to freely post.