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Altera_Forum
Honored Contributor
Honored ContributorVHDL "Quantum" bug
Hi all, I hope nobody has written about this before. I took a look but I found nothing... I'm a VHDL newbie and I'm facing an issue which is driving me crazy. The thing is that I have desi...
Altera_ForumHonored Contributor
Honored ContributorNot quite sure what you mean by "register loopback"? did you mean logic loops? logic loops are certainly a problem and can only be fixed by removing them.
