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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL PROCESS sensitivity help.

I have a VHDL process that seems to be going despite the sensitivity list. Right now, I'm trying to make one turn of a "simon says" game on the DE2 board. Here is the process giving me troubles. 

user_process : PROCESS(KEY3, KEY2, KEY1, KEY0)
BEGIN
IF user_turn = '1' THEN
	IF KEY3 ='0' OR KEY2 ='0' OR KEY1 ='0' OR KEY0 = '0' THEN
	CASE now_state IS
		
		WHEN USER_1 =>
						reg(0):= reg_val(0);
						reg(1):= reg_val(1);
						now_state <= USER_2;
						
		WHEN USER_2 =>
						reg(2):= reg_val(0);
						reg(3):= reg_val(1);
						now_state <= USER_3;
						
		WHEN USER_3 =>
						reg(4):= reg_val(0);
						reg(5):= reg_val(1);
						now_state <= USER_4;
						
		WHEN USER_4 =>
						reg(6):= reg_val(0);
						reg(7):= reg_val(1);
							IF reg = "11011000" THEN
							now_state <= DONE;
							ELSE
							now_state <= USER_1;
							END IF;
							
		WHEN DONE =>
		
						user_ledg_0 := '1';
						--user_turn := '0';
					
		WHEN OTHERS =>
						now_state <= USER_1;
						
	END CASE;
	END IF;
END IF;
END PROCESS user_process;

reg_val is a temporary register that changes values every time a pushbutton (KEY3-0) changes. user_ledg_0 is tied directly to a green LED. However, when the program gets to this process, the green light immediately turns on, without any pushbutton interaction seemingly ignoring the sensitivity list and IF statements. Quartus also doesn't complain of any syntax errors. Any help?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Sensitivity lists only apply for simulation. The Quartus synthesisor will ignore sensitivity lists when you compile the code. It uses the code inside the process to generate the logic.

    I see several problems here:

    1. User_turn and reg_val are missing from the sensitivity list.

    2. You are creating latches, not registers because you dont have a clock.

    3. What is reg? you're assigning it like a varaible but you dont have it declared in your process? I hope you're not using a shared variable.

    4. because of all of the above, Im not surprised its not working.

    You refer to the code as a program, and you say "when the program gets to this process". This show a misunderstanding of VHDL.

    1. VHDL is not a programming language.

    2. the process is always running - the "program" never "gets" to it because its always active. All processes run in parrall.

    I would think about starting again. before you write any code, think about the logic you are trying to create and draw it on some paper. When you have done this, re-write the VHDL describing (because VHDL is a description language, not a programming language) the behaviour of your circuit.