VHDL PROCESS sensitivity help.

Sensitivity lists only apply for simulation. The Quartus synthesisor will ignore sensitivity lists when you compile the code. It uses the code inside the process to generate the logic.

I see several problems here:

1. User_turn and reg_val are missing from the sensitivity list.

2. You are creating latches, not registers because you dont have a clock.

3. What is reg? you're assigning it like a varaible but you dont have it declared in your process? I hope you're not using a shared variable.

4. because of all of the above, Im not surprised its not working.

You refer to the code as a program, and you say "when the program gets to this process". This show a misunderstanding of VHDL.

1. VHDL is not a programming language.

2. the process is always running - the "program" never "gets" to it because its always active. All processes run in parrall.

I would think about starting again. before you write any code, think about the logic you are trying to create and draw it on some paper. When you have done this, re-write the VHDL describing (because VHDL is a description language, not a programming language) the behaviour of your circuit.