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Altera_Forum's avatar
Altera_Forum
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13 years ago

VHDL probably so simple you could do it in your sleep...but I can't

I need to write a code that "has two unsigned 6b inputs, inputa and inputb, and two outputs, multresult and iseven. multresult should give the result, without overflow, when the two inputs ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thanks Tricky, about the only error I realised so far is that I called the architecture rtl yet there isn't a single register.