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Altera_Forum's avatar
Altera_Forum
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13 years ago

VHDL probably so simple you could do it in your sleep...but I can't

I need to write a code that "has two unsigned 6b inputs, inputa and inputb, and two outputs, multresult and iseven. multresult should give the result, without overflow, when the two inputs ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity UNSIGNED_MULTIPLIER6x6 is
port (
       inputA, inputB : in unsigned(5 downto 0);
       multResult: out unsigned(11 downto 0);
      isEven: out STD_LOGIC
      );
end entity;
architecture rtl of UNSIGNED_MULTIPLIER6x6 is
signal Result: unsigned(11 downto 0);
begin
   Result <= inputA*inputB;
   multResult <= Result;
   isEven <= not Result(0);
end RTL ;