VHDL probably so simple you could do it in your sleep...but I can't

That's overkill (not sure it even works). Kaz already gave you the answer on a silver platter. VHDL and verilog you can multiply two signals together to get an output. The multiplier result width is the sum of the two input widths. For example if you multiply an 8-bit number by a 4-bit number you should ensure the wire/register that holds the result is 8+4 = 12 bits wide. Kaz also told you how to detect if a result is odd or even... if you don't believe him write some numbers in base 2 and look at the least significant bit.