VHDL probably so simple you could do it in your sleep...but I can't

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_UNSIGNED.all;

entity UNSIGNED_MULTIPLIER6x6 is

port (

inputA, inputB : in STD_LOGIC_VECTOR(5 downto 0);

multResult: out STD_LOGIC_VECTOR(11 downto 0));

isEven: out STD_LOGIC_VECTOR(1 downto 0);

end UNSIGNED_MULTIPLIER6x6;

architecture DATA_FLOW of UNSIGNED_MULTIPLIER6x6 is

multResult <= inputA*inputB;

if multResult0=1, then isEven<='0'

else isEven<= '1';

end if;

end process;

end DATA_FLOW ;