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Altera_Forum
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11 years ago

VHDL Partially Initialize in 0 a vector array

Im trying to create an array of vectors like shown in the code below: type ram256 is array (0 to 255) of std_logic_vector (11 downto 0); signal memoria: ram256; The problem is that, init...
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Altera_Forum
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11 years ago

You can initialize all bits using 


signal memoria: ram256 := (others => (others '0'));

You can use a similar statement at the beginning of a process to set the default state and then over-ride bits.

Cheers,

Dave